Asynchronously addressable clocked memory device and method of operating same

A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

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What is claimed is:

1. An integrated circuit memory device, comprising:

an external signal input for receiving an externally supplied address signal;

a timing circuit for providing a memory clock signal;

a memory array including a plurality of memory cells; and

an asynchronously addressable clocked memory controller communicating with said external signal input and said memory array and responsive to said timing circuit for receiving said externally supplied address asynchronously with respect to saidmemory clock signal and for accessing a selected memory cell associated with said externally supplied address synchronously with respect to said memory clock signal.

2. The device according to claim 1 wherein said asynchronously addressable clocked memory controller comprises:

a clocked memory control circuit responsive to said clock signal and communicating with said memory array for accessing said selected memory cell during an access cycle of said memory array; and

an asynchronous address buffer circuit communicating with said input for receiving said address asynchronously with respect to said clock signal and communicating with said clocked memory control circuit to apply said address to said clockedmemory control circuit.

3. The device according to claim 2 wherein said asynchronous address buffer circuit comprises: a first electronic storage element for storing a first one of said externally supplied addresses; and a second electronic storage element for storinga second one of said externally supplied addresses.

4. The device according to claim 3 wherein said first and second electronic storage elements comprise latches.

5. A device according to claim 2 wherein said asynchronous address buffer circuit comprises an address transition detector for proving an address detect signal upon receipt of said externally supplied address.

6. The device according to claim 5 wherein said asynchronous address buffer circuit comprises: an electronic storage element for storing said externally supplied address; an input switch between said input and said first electronic storageelement; and said address transition detector applies said address detect signal to said input switch.

7. The device according to claim 6 wherein said asynchronous address buffer circuit further comprises: an output switch between said first electronic storage element and said clocked memory control circuit; and a memory access cycle timerresponsive to said address detect signal for applying an address select signal to said output switch.

8. The device according to claim 7 wherein said asynchronous address buffer circuit further comprises:

a first said electronic storage element for storing a first externally supplied address and a second said electronic storage element for storing a second externally supplied address;

a first said input switch between said input and said first electronic storage element;

a second said input switch between said input and said second electronic storage element;

a first said output switch between said first electronic storage element and said clocked memory control circuit;

a second said output switch between said second electronic storage element and said clocked memory control circuit; and

said memory access cycle timer is responsive to a first said address detect signal for applying a first said address select signal to said first output switch, and is responsive to a second said address detect signal for applying a second saidaddress select signal to said second output switch.

9. The device according to claim 8 wherein said clocked memory control circuit accesses a first said selected memory cell associated with said first externally supplied address during a first said access cycle of said memory array, and accessesa second said selected memory cell associated with said second externally supplied address during a second said access cycle of said memory array.

10. The device according to claim 8 wherein said memory access cycle timer includes a delay circuit for delaying the application of said address select signal for a predetermined time after receiving said address detect signal.

11. The device according to claim 2 wherein said clocked memory control circuit accesses a first said selected memory cell associated with a first said asynchronously received address during a first access cycle of said memory array, andaccesses a second said selected memory cell associated with a second said asynchronously received address during a second access cycle of said memory array.

12. The device according to claim 2 wherein said access cycle includes a destructive read out cycle.

13. The device according to claim 1 wherein said memory cells include a ferroelectric memory element.

14. A ferroelectric integrated circuit memory device, comprising:

an external signal input for receiving an externally supplied address signal;

a timing circuit for providing a clock signal;

a memory array including a plurality of ferroelectric memory elements;

a clocked memory control circuit responsive to said clock signal and communicating with said memory array for synchronously accessing one of said memory cells during an access cycle of said memory array; and

an asynchronous address buffer circuit communicating with said input for receiving said address asynchronously with respect to said clock signal and for applying said address to said clocked memory control circuit.

15. The device according to claim 14 wherein said asynchronous address buffer circuit comprises an address transition detector.

16. An asynchronously addressable clocked controller, comprising;

a timing circuit for providing a clock signal;

a receiving circuit for receiving an externally supplied address asynchronously with respect to said clock signal; and

an output circuit for outputting said address synchronously with respect to said clock signal.

17. The controller according to claim 16 wherein said receiving circuit comprises an address transition detector.

18. The controller according to claim 16 wherein said receiving circuit comprises a first electronic storage element for storing a first one of said externally supplied addresses and a second electronic storage element for storing a second oneof said externally supplied addresses.

19. A method of operating an integrated circuit memory device including a memory array including a plurality of memory cells, the method comprising the steps of:

providing a clock signal;

receiving an externally supplied address asynchronously with respect to said clock signal; and

accessing a selected memory cell in said memory array associated with said address synchronously with respect to said clock signal.

20. The method according to claim 19, and further including the step of storing said address between said steps of receiving and accessing.

21. The method according to claim 20 wherein said step of storing is performed asynchronously with respect to said clock signal.

22. The method according to claim 20 wherein said step of storing comprises the steps of:

detecting a first address signal and producing a first address detect signal; and

routing said first address signal to an electronic storage element in response to said first address detect signal.

23. The method according to claim 22 wherein said step of storing further comprises the steps of:

detecting a further address signal and producing a further address detect signal; and

replacing said first address signal in said electronic storage element with said further address signal in response to said further address detect signal.

24. The method according to claim 22 wherein said step of accessing comprises the steps of:

producing an address select signal; and

routing said address signal to said memory array in response to said address select signal.

25. The method according to claim 19 wherein:

said step of receiving comprises receiving a first said address and a second said address; and

said step of accessing comprises accessing a first said selected memory cell associated with said first address in a first memory access cycle and accessing a second selected memory cell associated with said second address in a second memoryaccess cycle.

26. The method according to claim 19 wherein said step of accessing comprises the steps of:

reading said selected memory cell to change its state from a first logical state to a second logical state; and then restoring said selected memory cell to said first logical state.

27. The method according to claim 26 wherein said plurality of memory cells comprises a plurality of ferroelectric memory elements, and wherein:

said step of reading comprises the step of changing said ferroelectric memory element of said selected memory cell from a first polarization state to a second polarization state; and

said step of restoring comprises the step of restoring said ferroelectric memory element of said selected memory cell to said first polarization state.

28. The method of operating an asynchronously addressable clocked controller, said method comprising the steps of:

providing a clock signal;

receiving an externally supplied address asynchronously with respect to said clock signal; and

outputting said address synchronously with respect to said clock signal.

29. The method according to claim 28, and further including the step of storing said address between said steps of receiving and outputting.

30. The method according to claim 29 wherein said step of storing is performed asynchronously with respect to said clock signal.

31. The method according to claim 29 wherein said step of storing comprises the steps of:

detecting a first address signal transition and producing a first address detect signal; and

routing said first address signal to an electronic storage element in response to said first address detect signal.

32. The method according to claim 31 wherein said step of storing further includes the step of delaying the routing of said first address signal for a predetermined time after said step of detecting.

33. The method according to claim 31 wherein said step of storing further comprises the steps of:

detecting a further address signal transition and producing a further address detect signal; and

replacing said first address signal in said electronic storage element with said her address signal in response to said further address detect signal.

34. The method according to claim 28 wherein said step of outputting comprises the steps of:

detecting an address signal transition and producing an address detect signal;

producing an address select signal in response to said address detect signal; and

outputting said address signal in response to said address select signal.