Circuit and method for reducing jitter in a PLL of high speed serial links

Citations

2003/0080817 5343167 5422603 5463352 5495207 5650754 5783972 5807003 5903195 5959502 6097244 6292061 6977558

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Claims:

What is claimed is:

1. A circuit for reducing jitter in a high speed serial link, the circuit comprising: a phase-locked loop (PLL), the PLL comprising a voltage controlled oscillator (VCO); aregulator coupled to the PLL to provide a supply voltage to the PLL; and a regulator control circuit coupled to the PLL and to the regulator for examining at least one parameter related to performance of the VCO, including a VCO control voltage, and forcontrolling adjustments of the supply voltage based on the examination.

2. The circuit of claim 1 wherein the regulator control circuit further determines if the VCO control voltage is within a predetermined range of optimum operation.

3. The circuit of claim 2 wherein the regulator control circuit further examines a lock status of the PLL.

4. The circuit of claim 3 wherein when the VCO control voltage is within the predetermined range and the PLL is locked, no adjusting of the supply voltage is done.

5. The circuit of claim 4 wherein when the VCO control voltage is not within the predetermined range or the PLL is not locked, the supply voltage is adjusted.

6. The circuit of claim 5 wherein the regulator control circuit further controls selection of a voltage level output from the regulator.

7. The circuit of claim 1 wherein the regulator control circuit comprises a band gap-based reference generator coupled to comparator logic, the comparator logic coupled to measurement logic, and decision logic coupled to the measurement logicand to the comparator logic.

8. A regulator control circuit for reducing jitter in a high speed serial link, the circuit comprising: decision logic for examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in a phase-locked loop(PLL), including a VCO control voltage, comparator logic coupled to the decision logic for comparing the VCO control voltage to predetermined voltage levels, and controlling adjustments of a supply voltage to the VCO based on the examining.

9. The regulator control circuit of claim 8 further comprising a band gap-based reference generator for establishing the predetermined voltage levels.

10. The regulator control circuit of claim 8 further comprising measurement logic coupled to the comparator logic for measuring an output of the comparator logic against a predetermined range of optimum operation and providing an indicatorsignal to the decision logic.

11. The regulator control circuit of claim 10 wherein the decision logic further examines a lock status of the PLL.

12. The regulator control circuit of claim 11 wherein when the decision logic determines that the VCO control voltage is within the predetermined range based on the indicator signal and that the PLL is locked based on the lock status, noadjusting of the supply voltage is done.

13. The regulator control circuit of claim 12 wherein when the decision logic determines that VCO control voltage is not within the predetermined range or the PLL is not locked, the supply voltage is adjusted.

14. The regulator control circuit of claim 8 wherein the decision logic further controls selection of a voltage level output of a regulator supplying voltage to the VCO.

15. A method for reducing jitter in a phase-locked loop (PLL) of a high speed serial link, the method comprising: (a) examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, including a VCOcontrol voltage; and (b) controlling adjustment of a supply voltage to the VCO based on the examining.

16. The method of claim 15 wherein the examining step (a) further comprises determining if the VCO control voltage is within a predetermined range of optimum operation.

17. The method of claim 16 wherein the examining step (a) further comprises examining a lock status of the PLL.

18. The method of claim 17 wherein when the VCO control voltage is within the predetermined range and the PLL is locked, no adjusting of the supply voltage is done.

19. The method of claim 18 wherein when the VCO control voltage is not within the predetermined range or the PLL is not locked, the supply voltage is adjusted.

20. The method of claim 15 wherein controlling step (b) further comprises controlling selection of a voltage level output of a regulator supplying voltage to the VCO.

Patent number:
7042277
View patent at USPTO

Filing date:
October 14, 2003

Issue date:
May 9, 2006

Inventors:
Hayden C. Cranford, Jr. (Cary, NC)
Vernon R. Norman (Cary, NC)
Stacy J. Garvin (Durham, NC)
Todd M. Rasmus (Cary, NC)

Assignee:
International Business Machines Corporation (Armonk, NY)

Primary Examiner:
Minh Nguyen

Attorney, Agent or Firm:
Sawyer Law Group LLP

Current U.S. Classification: 327/538 331/185