H-bridge power amplifier for a motor

A highly linear, low-distortion H-bridge amplifier is described. The amplifier includes four interconnected power transistors connected to an inductive load. Each transistor has a precision voltage clamp connected between the source and drain to suppress ringing oscillations. Two or more of the transistors also include high-speed transient-voltage suppressers connected in parallel with their respective voltage clamps. These transient-voltage suppressers do not have the clamping accuracy of the voltage clamps, but respond much more quickly to suppress noise spikes. The amplifier therefore takes advantage of both the fast response time of the transient-voltage suppressers and the precise voltage-clamping characteristics of the voltage clamps.

If you were to search for H-bridge power amplifier for a motor using relaxed search criteria, these patents would come up:

What is claimed is:

1. An amplifier for driving a load, the amplifier comprising:

first and second input nodes;

a first transistor having a control terminal connected to the first input node, a first current-handling terminal connected to a first voltage potential, and a second current-handling terminal connected to the load;

a second transistor having a control terminal connected to the second input node, a first current-handling terminal connected to the load, and a second current-handling terminal connected to a second voltage potential;

a voltage clamp connected between the first and second current-handling terminals of the first transistor, the voltage clamp having a voltage clamp response time; and

a transient-voltage suppresser connected between the first and second current-handling terminals of the second transistor, the transient-voltage suppresser having a transient-voltage suppresser response time that is smaller than the voltage clampresponse time.

2. The amplifier of claim 1, further comprising a second voltage clamp connected between the first and second terminals of the second transistor.

3. The amplifier of claim 1, further comprising a second transient-voltage suppresser connected between the first and second terminals of the first transistor.

4. The amplifier of claim 1, wherein the load comprises an inductance.

5. The amplifier of claim 1, wherein the transistors are power MOSFET transistors.

6. The amplifier of claim 1, further comprising:

a third transistor having a control terminal connected to a third input node, a first current-handling terminal connected to the first voltage potential, and a second current-handing terminal connected to the load; and

a fourth transistor having a control terminal connected to a fourth input node, a first current-handling terminal connected to the load, and a second current-handing terminal connected to the second voltage potential.

7. The amplifier of claim 6, further comprising:

a second voltage clamp connected between the first and second current-handling terminals of the third transistor; and

a second transient-voltage suppresser connected between the first and second current-handling terminals of the fourth transistor.

8. The amplifier of claim 7, wherein the second voltage clamp and second transient-voltage suppresser have respective response times, and wherein the second-voltage-clamp response time is greater than the second-transient-voltage-suppresserresponse time.

9. The amplifier of claim 7, further comprising a third voltage clamp connected between the first and second terminals of the fourth transistor.

10. The amplifier of claim 7, further comprising a third transient-voltage suppresser connected between the first and second terminals of the third transistor.

11. An amplifier for driving a load, the amplifier comprising:

first and second input nodes;

a first transistor having a control terminal connected to the first input node, a first current-handling terminal connected to a first voltage potential, and a second current-handing terminal connected to the load;

a second transistor having a control terminal connected to the second input node, a first current-handling terminal connected to the load, and a second current-handing terminal connected to a second voltage potential;

first noise-suppression means connected between the first and second current-handling terminals of the first transistor, the noise-suppression means having a first response time; and

second noise-suppression means connected between the first and second current-handling terminals of the second transistor, the second noise-suppression means having a second response time smaller than the first response time.

12. The amplifier of claim 11, wherein the load comprises an inductance.

13. The amplifier of claim 11, wherein the transistors are MOSFET transistors.

14. The amplifier of claim 11, further comprising:

a third transistor having a control terminal connected to a third input node, a first current-handling terminal connected to the first voltage potential, and a second current-handing terminal connected to the load; and

a fourth transistor having a control terminal connected to a fourth input node, a first current-handling terminal connected to the load, and a second current-handing terminal connected to the second voltage potential.

15. The amplifier of claim 14, further comprising:

a third noise-suppression means connected between the first and second current-handling terminals of the third transistor; and

a fourth noise-suppression means connected between the first and second current-handling terminals of the fourth transistor.

16. The amplifier of claim 15, wherein the third noise-suppression means has a third response time and the fourth noise-suppression means has a fourth response time, and wherein the third response time is greater than the fourth responsetime.