Memory module device formation and mounting methods thereof

Abstract:

In a memory module arranged with the connection terminals located on both sides of the circuit board, the connection terminals for transmitting a common signal to all memory modules conducts with the connection terminals that are directly facing each other on the opposite sides of the circuit board, and the connection terminals for transmitting an intrinsic signal to the respective memory modules conduct with connection terminals that are not directly facing each other through the circuit board.

Citations
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7009848 Method, adapter card and configuration for an installation of memory modules 2006-03-07
7045891 Sockets for module extension and memory system using same 2006-05-16
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Claims:

What is claimed:

1. A memory module comprising: a circuit board on which a memory chip is mounted; a plurality of connection terminals which are provided at locations on both sides of saidcircuit board for passing a signal with said memory chip through said connection terminals; said connection terminals including a first connection terminal group for passing a specific signal in said memory chip, and a second connection terminal groupfor passing other signals; said connection terminals of said first connection terminal group being configured such that connection terminals on both sides of said circuit board that are facing each other through said circuit board are not electricallyconnected; and said connection terminals of said second connection terminal group being configured such that connection terminals on both sides of said circuit board that are facing each other through said circuit board are electrically connected.

2. A memory module according to claim 1, further comprising at least one additional memory module, said memory modules being laminated into a body, said laminated body including superimposed memory modules having connection terminals on adjacentmemory modules facing one another; wherein said connection terminals facing one another on adjacent memory modules are electrically connected with each other.

3. A laminated body of memory modules according to claim 2, wherein said laminated body of memory modules is mounted on a device body.

4. A laminated body of memory modules according to claim 3, wherein at least one connector for use in attaching said memory modules is mounted thereon.

5. A laminated body of memory modules according to claim 4, wherein each memory module is mounted on a circuit board, said circuit board comprising a flexible board.

6. A laminated body according to claim 4, wherein said connection terminals are electrically connected together by sandwiching said at least one connector.

7. A laminated body of memory modules according to claim 5, said laminated body memory modules having connection terminals facing one another on adjacent memory modules, said connection terminals facing one another on adjacent memory modulesbeing electrically coupled together by sandwiching said modules together.

8. A laminated body of memory modules according to claim 2, wherein an anisotropic conduction adhesive member is located between said connection terminals facing one another on adjacent memory modules.

9. A laminated body of memory modules according to claim 2, each memory module coupled to a circuit board, further comprising: a connector for sandwiching said memory modules; at least one first part for use in fitting memory modules together,said first part being provided with said connector; and at least one second part for use in fitting each memory module to its circuit board, said second part being provided with said circuit board; wherein said connection terminals facing one anotheron adjacent memory modules are electrically coupled with each other by fitting said first part with said second part.

10. A memory card, comprising a memory module according to claim 1.

11. A computer, comprising a memory module according to claim 1.

12. A memory module as in claim 1, wherein said connection terminals of said first connection terminal group are electrically connected to connection terminals on the other side of the circuit board that are adjacent to said connection terminalsthat are facing each other through said circuit board.

13. A laminated body of memory modules comprising memory chips and connection terminals for passing one or more signals between a memory chip and a device body, said connection terminals including a first group of connection terminals forpassing a specific signal to a specific memory chip, said first group of connection terminals facing one another from overlapping memory modules and being electrically connected to each other, a second group of connection terminals for passing othersignals to said memory chips as common signal lines, said second group of connection terminals facing one another from overlapping memory modules and being electrically connected to each other, and said common signal lines being connected to said devicebody.

14. A laminated body of memory modules comprising memory chips and connection terminals, said laminated body being coupled to a device body, said connection terminals including first connection terminals for passing a specific signal to aspecific memory module chip, said first connection terminals being individually connected to said device body from said specific memory module, said connection terminals including second connection terminals that are facing one another from overlappingmemory modules in said laminated body, said second connection terminals facing each other being electrically connected to each other as a common signal line, and said common signal line being connected to said device body.

15. A memory device comprising: a first memory module including: a circuit board having top and bottom surfaces; at least one memory chip on at least one of said top and bottom surfaces; a plurality of top surface connection terminals disposedon said top surface and a plurality of bottom surface connection terminals disposed on said bottom surface; wherein a first group of said plurality of connection terminals includes first group top surface connection terminals in electrical contact withand located directly above first group bottom surface connection terminals; and a second group of said plurality of connection terminals includes second group top surface connection terminals in electrical contact with second group bottom surfaceconnection terminals that are not directly below said top surface connection terminals.

16. A memory device as in claim 15, wherein said second group of said plurality of connection terminals includes second group top surface connection terminals in electrical contact with and located diagonally above second group bottom surfaceconnection terminals.

17. A memory device as in claim 15, further comprising: a second memory module having the same connection terminal structure as said first memory module, wherein said second memory module is stacked directly over said first memory module; andsaid bottom surface connection terminals of said second memory module are electrically connected to the adjacent top surface connection terminals of said first memory module.

18. A memory device as in claim 17, further comprising additional memory modules stacked over said second memory module.

19. A memory device as in claim 15, wherein said circuit board comprises a flexible material.

20. A method for forming a memory device comprising: providing a plurality of memory modules having top and bottom surfaces and top and bottom connection terminals, each memory module including a first connection terminal group including firsttop surface connection terminals in electrical contact with and located directly above first bottom surface connection terminals, and a second connection terminal group including second top surface connection terminals in electrical contact with secondbottom surface connection terminals that are not directly below said second top surface connection terminals; and stacking at least two of said memory modules so that the top connection terminals from a first memory module are directly aligned with andelectrically coupled to the bottom connection terminals of a second memory module.

21. A method as in claim 20, further comprising the step of providing a conducting adhesive between the connection terminals of adjacent memory modules.

22. A method as in claim 20, further comprising providing at least one connector and sandwiching said memory modules within said connector.

23. A memory module comprising: a circuit board on which a memory chip is mounted on a surface thereof; a plurality of connection terminals which are provided at locations on opposite sides of the circuit board; the connection terminalsincluding a first connection terminal group having terminals on opposite sides of a portion of the circuit board and a second connection terminal group having terminals on opposite sides of a portion of the circuit board; the first connection terminalgroup including connection terminals on opposite sides of the circuit board that are directly aligned with one another when viewed from a direction perpendicular to the circuit board surface, wherein the connection terminals of the first connectionterminal group on opposite sides of the circuit board that are directly aligned with one another are not in electrical contact with each other; and the second connection terminal group including- connection terminals on opposite sides of the circuitboard that are directly aligned with one another when viewed from a direction perpendicular to the circuit board surface, wherein the connection terminals of the second connection terminal group on opposite sides of the circuit board that are directlyaligned with one another are electrically connected through the circuit board.

24. A memory module as in claim 23, wherein a plurality of the connection terminals of the first connection terminal group-are electrically connected to connection terminals on an opposite side of the circuit board that are adjacent to thedirectly aligned connection terminals.

Patent number:
    6542373
View patent at USPTO

Filing date:
    November 3, 1998

Issue date:
    April 1, 2003

Inventor:
Ryo Oba (Suwa, JP)

Assignee:
Seiko Epson Corporation (Tokyo, JP)

Primary Examiner:
Jayprakash N. Gandhi

Attorney, Agent or Firm:
Konrad Raynes Victor & Mann, LLPRaynes; Alan S.

Current U.S. Classification: 174/261 361/735 361/760 361/777 361/778 361/784 361/803

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