Non-volatile mass storage cache coherency apparatus

Abstract:

Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Citations

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Cited By

Patent number	Title	Issue date
7103724	Method and apparatus to generate cache data	2006-09-05
7233880	Adaptive cache algorithm for temperature sensitive memory	2007-06-19

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Claims:

What is claimed is:

1. A controller to determine if there is coherency between a mass-storage device and a cache, wherein the controller is to flush the cache and operate the cache in awrite-through mode based on receipt of an indication that the mass-storage device or the cache is to be physically disconnected from the system, and wherein the controller is to change the cache from write-through mode to write-back mode based on thecache having been physically reconnected to a mass-storage device.

2. The controller of claim 1, wherein the controller is coupled to a display to provide an indication to a user whether it is safe from a data-coherency standpoint to physically disconnect the mass-storage device or the cache from the system.

3. The controller of claim 1, wherein the cache is a non-volatile cache.

4. The controller of claim 3, wherein the non-volatile cache is a ferro-electric RAM.

5. The controller of claim 1, wherein the display is selected from the group consisting of a light emitting diode, a bi-state light emitting diode, and a liquid crystal display.

6. The controller of claim 1, wherein the apparatus further comprises an input to receive an indication from a user that the system should be made safe from a data-coherency standpoint to physically disconnect the mass-storage device or thecache from the system.

7. A system comprising: a mass-storage device; a non-volatile cache; a controller to determine if there is coherency between the mass-storage device and the cache, wherein the controller is to flush the cache and operate the cache in awrite-through mode based on receipt of an indication that the mass-storage device or the cache is to be physically disconnected from the system.

8. The system of claim 7, wherein the system further comprises a display coupled to the controller to provide an indication to a user whether it is safe from a data-coherency standpoint to physically disconnect the mass-storage device or thecache from the system.

9. The system of claim 8, wherein the cache is a non-volatile cache.

10. The system of claim 9, wherein the non-volatile cache is a ferro-electric RAM.

11. The system of claim 7, wherein the display is selected from the group consisting of a light emitting diode, a bi-state light emitting diode, and a liquid crystal display.

12. The system of claim 7, wherein the apparatus further comprises an input to receive an indication from a user that the system should be made safe from a data-coherency standpoint to physically disconnect the mass-storage device or the cachefrom the system.

13. A method of administering coherency in a system with a mass-storage device and a cache, the method comprising: receiving an indication from a user that the system should be made safe from a data-coherency standpoint to physically disconnectthe mass-storage device or the cache from the system; flushing the cache and changing the cache to a write-through mode based on receipt of said indication that the system should be made safe from a data-coherency standpoint to physically disconnect themass-storage device or the cache from the system; determining that the cache has been physically reconnected to a mass-storage device; and changing the cache from write-through mode to write-back mode based on the cache having been physicallyreconnected to the mass-storage device.

14. The method of claim 13, wherein the method further comprises displaying an indication that it is safe from a data-coherency standpoint to physically disconnect the mass-storage device or the cache from the system.

15. The method of claim 13, wherein the indication is displayed using one of a light emitting diode, a bi-state light emitting diode, or a liquid crystal display.

16. The apparatus of claim 13, wherein the cache is a ferro-electric RAM.

Patent number:
6941423
View patent at USPTO

Filing date:
December 22, 2003

Issue date:
September 6, 2005

Inventor:
Richard L. Coulson (Portland, OR)

Assignee:
Intel Corporation (Santa Clara, CA)

Primary Examiner:
Nasser Moazzami

Attorney, Agent or Firm:
Kenyon & Kenyon

Current U.S. Classification: 711/135 711/141 711/142 711/143