Signal generator circuit and level shifter with signal generator circuit

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What is claimed is:

1. A signal generator circuit comprising: an output adjustor circuit for outputting a first output signal and a second output signal in accordance with an input signal; anda level shifter unit for converting a voltage level in accordance with the input signal to output a third output signal and a fourth output signal, wherein in response to a rising of the input signal, the first output signal first changes, the third andfourth output signals change subsequently, and then the second output signal changes, and in response to a falling of the input signal, the second output signal first changes, the third and fourth output signals change subsequently, and then the firstoutput signal changes.

2. A signal generator circuit according to claim 1 wherein the third output signal and the fourth output signal are opposite to each other.

3. A signal generator circuit according to claim 1, wherein the third and fourth output signals have an amplitude larger than an amplitude of the first and second output signals.

4. A signal generator circuit according to claim 1, wherein the first and second output signals are in a low voltage output region, while the third and fourth output signals are in a high voltage output region.

5. A signal generator circuit according to claim 2, wherein the first and second output signals are in a low voltage output region, while the third and fourth output signals are in a high voltage output region.

6. A signal generator circuit according to claim 3, wherein the first and second output signals are in a low voltage output region, while the third and fourth output signals are in a high voltage output region.

7. A signal generator circuit according to claim 1, wherein said output adjustor circuit generates the first output signal in accordance with an inverted version of the input signal and a delayed version of the second output signal, andgenerates the second output signal in accordance with the input signal and a delayed version of the first output signal.

8. A signal generator circuit according to claim 7, wherein: the inverted version of the input signal and the delayed version of the second output signal are applied to a first NAND element, the output of which is the first output signal; andthe input signal and the delayed version of the first output signal are applied to a second NAND element, the output of which is the second output signal.

9. A signal generator circuit according to claim 1, wherein said output adjustor circuit outputs the first and second output signals based on the third and fourth output signals.

10. A signal generator circuit according to claim 9, wherein said output adjustor circuit generates the first output signal in accordance with the input signal and the third output signal, and generates the second output signal in accordancewith the input signal and the fourth output signal.

11. A signal generator circuit according to claim 10, wherein: the input signal and the third output signal are applied to a third NAND element, the output of which is the first output signal; and the input signal and the fourth output signalare applied to a fourth NAND element, the output of which is the second output signal.

12. A signal generator circuit according to claim 11, wherein said third NAND element is applied with an inverted version of the input signal and the third output signal, and said fourth NAND element is applied with an inverted version of thefourth output signal.

13. A signal generator circuit having an output adjustor circuit for generating an output signal at a low voltage level, and a level shifter unit for generating an output at a high voltage level, wherein: said level shifter unit comprises afirst delay element, a first low voltage inverter, a high voltage power supply, a ground potential, a first and a second high voltage side output terminal, a first and a second high voltage P-ch transistor, a first and second high voltage inverter, and afirst and a second high voltage N-ch transistor, said first delay element having an input side connected to an input terminal for receiving an input signal, and an output side connected to an input side of said first low voltage inverter and to a gate ofsaid first high voltage N-ch transistor; said first high voltage P-ch transistor having a source connected to said high voltage power supply, a gate branched for connection to a line which connects a drain of said second high voltage P-ch transistorwith a drain of said second high voltage N-ch transistor, and a drain connected to a drain of said first high voltage N-ch transistor; said second high voltage P-ch transistor having a source connected to said high voltage power supply, a gate branchedfor connection to a line which connects the drain of said first high voltage P-ch transistor with a drain of said first high voltage N-ch transistor, and the drain connected to the drain of said second high voltage N-ch transistor; said first highvoltage N-ch transistor having a source connected to said ground potential, the gate branched for connection to a line which connects the other end side of said first delay element with the input side of said first low voltage inverter, and the drainconnected to the drain of said first high voltage P-ch transistor; said second high voltage N-ch transistor having a source connected to said ground potential, a gate connected to an output side of said first low voltage inverter, and the drainconnected to the drain of said second high voltage P-ch transistor; said first high voltage side output terminal being branched for connection to a line which connects the drain of said first high voltage P-ch transistor with the drain of said firsthigh voltage N-ch transistor through said first high voltage inverter; and said second high voltage side output terminal being branched for connection to a line which connects the drain of said second high voltage P-ch transistor with the drain of saidsecond high voltage N-ch transistor through said second high voltage inverter, and said output adjustor circuit comprises an input terminal for receiving an input signal, a first and a second low voltage side output terminal, a plurality of delayelements, a second low voltage inverter, and a first and a second low voltage NAND element; said first low voltage NAND element having one input side connected to said input terminal through said second low voltage inverter, and the other input sidebranched for connection to a line which connects an output side of said second low voltage NAND element with said second low voltage side output terminal through a plurality of delay elements; and said second low voltage NAND element having one inputside branched for connection to a line which connects the output side of said first low voltage NAND element with said first low voltage side output terminal, and the other input side connected to said input terminal.

14. A signal generator circuit having an output adjustor circuit for generating an output signal at a low voltage level, and a level shifter unit for generating an output at a high voltage level, wherein: said level shifter unit comprises afirst delay element, a first low voltage inverter, a high voltage power supply, a ground potential, a first and a second high voltage side output terminal, a first and a second high voltage P-ch transistor, a first and second high voltage inverter, and afirst and a second high voltage N-ch transistor, said first delay element having an input side connected to an input terminal for receiving an input signal, and an output side connected to an input side of said first low voltage inverter and to a gate ofsaid first high voltage N-ch transistor; said first high voltage P-ch transistor having a source connected to said high voltage power supply, the gate branched for connection to a line which connects a drain of said second high voltage P-ch transistorwith a drain of said second high voltage N-ch transistor, and a drain connected to a drain of said first high voltage N-ch transistor; said second high voltage P-ch transistor having a source connected to said high voltage power supply, a gate branchedfor connection to a line which connects the drain of said first high voltage P-ch transistor with the drain of said first high voltage N-ch transistor, and the drain connected to the drain of said second high voltage N-ch transistor; said first highvoltage N-ch transistor having a source connected to said ground potential, a gate branched for connection to a line which connects the other end side of said first delay element with the input side of said first low voltage inverter, and the drainconnected to the drain of said first high voltage P-ch transistor; said second high voltage N-ch transistor having a source connected to said ground potential, a gate connected to an output side of said first low voltage inverter, and the drainconnected to the drain of said second high voltage P-ch transistor; said first high voltage side output terminal being branched for connection to a line which connects the drain of said first high voltage P-ch transistor with the drain of said firsthigh voltage N-ch transistor through said first high voltage inverter; and said second high voltage side output terminal being branched for connection to a line which connects the drain of said second high voltage P-ch transistor with the drain of saidsecond high voltage N-ch transistor through said second high voltage inverter, and said output adjustor circuit comprises an input terminal for receiving an input signal, a first and a second low voltage side output terminal, a second low voltageinverter, a third and a fourth high voltage inverter, and a first and a second low voltage NAND element; said first low voltage NAND element having one input side connected to said input terminal through said second low voltage inverter, and anotherinput side branched for connection to a line which connects an output side of said first high voltage inverter with said first high voltage side output terminal through said third high voltage inverter; said second low voltage NAND element having oneinput side branched for connection to a line which connects an output side of said second high voltage inverter through said fourth high voltage inverter, and the other input side connected to said input terminal.

15. A level shifter having a signal generator circuit, comprising: a signal generator circuit having an output adjustor circuit for outputting a first output signal and a second output signal in accordance with an input signal, and a levelshifter unit for converting a voltage level in accordance with the input signal to output a third output signal and a fourth output signal, wherein in response to a rising of the input signal, the first output signal first changes, the third and fourthoutput signals next change, and then the second output signal changes, and in response to a falling of the input signal, the second output signal first changes, the third and fourth output signals change, and then the first output signal changes; and alevel shifter for outputting a first and a second amplified output signal, the voltage level of which is amplified, said first and second amplified output signals simultaneously transitioning to "H" level or "L" level based on one of the first and secondoutput signals and one of the third and fourth output signals of said signal generator circuit.

16. A level shifter having a signal generator circuit according to claim 15, wherein: one of the third and fourth output signals of said signal generator circuit used by said level shifter is a signal which change in a reverse direction to oneof the first and second output signals of said signal generator circuit.

17. A level shifter having a signal generator circuit according to claim 16, wherein: said level shifter comprises a first and a second low voltage NAND element, a high voltage power supply, a ground potential, a first to a fourth P-chtransistor, a first and a second output terminal for outputting said first and second amplified output signals, respectively, a first and a second high voltage N-ch transistor, said first low voltage NAND element having one input side connected to aninput terminal for receiving a second input signal, and the other input side connected to an output terminal for outputting a second output signal; said second low voltage NAND element having one input side connected to an output side of said first lowvoltage NAND element, and the other input side connected to an output terminal for outputting one of the first and second output signals of said signal generator circuit; said first high voltage P-ch transistor having a source connected to said highvoltage power supply, a gate connected to an output terminal for outputting one of the third and fourth output signals of said signal generator circuit, and a drain connected to a source of said second high voltage P-ch transistor; said second highvoltage P-ch transistor having the source connected to the drain of said first high voltage P-ch transistor, a gate branched for connection to a line which connects a drain of said fourth high voltage P-ch transistor with a drain of said second highvoltage N-ch transistor, and a drain connected to the drain of said first high voltage N-ch transistor; said third high voltage P-ch transistor having a source connected to said high voltage power supply, a gate connected to said output terminal foroutputting one of the third and fourth output signals of said signal generator circuit, and a drain connected to a source of said fourth high voltage P-ch transistor; said fourth high voltage P-ch transistor having the source connected to the drain ofsaid third high voltage P-ch transistor, a gate branched for connection to a line which connects the drain of said second high voltage P-ch transistor with the drain of said first high voltage N-ch transistor, and the drain connected to the drain of saidsecond high voltage N-ch transistor; said first high voltage N-ch transistor having a source connected to said ground potential, a gate branched for connection to a line which connects the output side of said first low voltage NAND element with oneinput side of said second low voltage NAND element, and the drain connected to the drain of said second high voltage P-ch transistor; and said second high voltage N-ch transistor having a source connected to said ground potential, a gate connected tothe output side of said second low voltage NAND element, and the drain connected to the drain of said fourth high voltage P-ch transistor; said first output terminal being branched for connection to a line which connects the drain of said second highvoltage P-ch transistor with the drain of said first high voltage N-ch transistor; and said second output terminal being branched for connection to a line which connects the drain of said fourth high voltage P-ch transistor with the drain of said secondhigh voltage N-ch transistor.

18. A level shifter having a signal generator circuit according to claim 16, wherein: said level shifter comprises a first and a second low voltage NOR element, a high voltage power supply, a ground potential, a first to a fourth high voltageP-ch transistor, a first and a second output terminal, and a first and a second high voltage N-ch transistor, said first low voltage NOR element having one input terminal connected to an input terminal for receiving a second input signal, and the otherinput side connected to an output terminal for outputting one of the first and second output signals of said signal generator circuit; said second low voltage NOR element having one input side connected to an output side of said first low voltage NORelement, and the other input side connected to the output terminal for outputting one of the first and second output signals of said signal generator circuit-; said first high voltage P-ch transistor having a source connected to said high voltage powersupply, a gate connected to an output terminal for outputting one of the third and fourth output signals of said signal generator circuit, and-a drain branched for connection to a line which connects a drain of said second high voltage P-ch transistorwith a drain of said first high voltage N-ch transistor; said second high voltage P-ch transistor having a source connected to said high voltage power supply, a gate branched for connection to a line which connects a drain of said third high voltageP-ch transistor with a drain of said second high voltage N-ch transistor, and a drain connected to the drain of said first high voltage N-ch transistor; said third high voltage P-ch transistor having a source connected to said high voltage power supply,a gate branched for connection to a line which connects the drain of said second high voltage P-ch transistor with the drain of said first high voltage N-ch transistor, and a drain connected to the drain of said second high voltage N-ch transistor; saidfourth high voltage P-ch transistor having a source connected to said high voltage power supply, a gate connected to the output terminal for outputting one of the third and fourth output signals of said signal generator circuit, and a drain branched forconnection to a line which connects the drain of said third high voltage P-ch transistor with the drain of said second high-voltage N-ch transistor; said first high voltage N-ch transistor having a source connected to said ground potential, a gatebranched for connection to a line which connects the output side of said first low voltage NOR element with the one input side of said second low voltage NOR element, and a drain branched for connection to the drains of said first and second high voltageP-ch transistors; said second high voltage N-ch transistor having a source connected to said ground potential, a gate connected to the output side of said second low voltage NOR element, and the drain branched for connection to the drains of said firstand second high voltage P-ch transistors; said first output terminal being branched for connection to a line which connects the drains of said first and second high voltage P-ch transistors with the drain of said first high voltage N-ch transistor; andsaid second output terminal being branched for connection to a line which connects the drains of said third and fourth high voltage P-ch transistors with the drain of said second high voltage N-ch transistor.